Concurrent BIST for Embedded SRAMs in SoCs

With the progress of deep submicron technology and increasing design complexity, hundreds of memory cores with different size and configuration are embedded in system-on-chips (SoCs). These memory cores occupy a noticeable silicon area and need an efficient and low-cost test methodology. Built-in Self-test (BIST) is a practical solution provides a certain degree of reliability and flexibility. However, designing a memory BIST circuit is a considerable task which imposes some limitations to the designer. These limitations can be grouped in three categories: area overhead, test and diagnosis time and fault coverage. This paper proposes an at-speed and parallel BIST scheme based on IEEE std 1500 for concurrent testing of all SRAM memories embedded in a SoC. A novel structure of IEEE std 1500 wrapper, supports at-speed and parallel testing which reduces the test time. Also by including an algorithm analyzer, we can apply every march algorithm to the BIST circuit which results to a high fault coverage. Finally, sharing method for homogeneous memories improves the area overhead of the design.